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PIC18F85J11 FAMILY

DS39774D-page 172

2010 Microchip Technology Inc.

16.2

Capture Mode

In Capture mode, the CCPR2H:CCPR2L register pair

captures the 16-bit value of the TMR1 or TMR3 register

when an event occurs on the CCP2 pin (RB3, RC1 or

RE7, depending on device configuration). An event is

defined as one of the following:

every falling edge

every rising edge

every 4th rising edge

every 16th rising edge

The event is selected by the mode select bits,

CCP2M<3:0> (CCP2CON<3:0>). When a capture is

made, the interrupt request flag bit, CCP2IF (PIR3<2>),

is set; it must be cleared in software. If another capture

occurs before the value in register CCPR2 is read, the

old captured value is overwritten by the new captured

value.

16.2.1

CCPx PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

16.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchronized Counter mode. In Asynchronous Counter

mode, the capture operation may not work. The timer to

be used with each CCP module is selected in the T3CON

register (see Section 16.1.1 “CCP Modules and Timer

Resources”).

16.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP2IE bit (PIE3<2>) clear to avoid false interrupts

and should clear the flag bit, CCP2IF, following any

such change in operating mode.

16.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode.

They are specified as part of the operating mode

selected by the mode select bits (CCP2M<3:0>).

Whenever the CCP2 module is turned off, or the CCP2

module is not in Capture mode, the prescaler counter

is cleared. This means that any Reset will clear the

prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

a non-zero prescaler. Example 16-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 16-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 16-2:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Note: If RB3/INT3/CCP2, RC1/T1OSI/CCP2 or

RE7/CCP2 is configured as an output, a write

to the port can cause a capture condition.

CLRF

CCP2CON

; Turn CCP module off

MOVLW NEW_CAPT_PS

; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP2CON

; Load CCP2CON with

; this value

CCPR1H

CCPR1L

TMR1H

TMR1L

Set CCP1IF

TMR3

Enable

Q1:Q4

CCP1CON<3:0>

CCP1 Pin

Prescaler

1, 4, 16

and

Edge Detect

TMR1

Enable

T3CCP2

CCPR2H

CCPR2L

TMR1H

TMR1L

Set CCP2IF

TMR3

Enable

CCP2CON<3:0>

CCP2 Pin

Prescaler

1, 4, 16

TMR3H

TMR3L

TMR1

Enable

T3CCP2

T3CCP1

T3CCP2

T3CCP1

TMR3H

TMR3L

and

Edge Detect

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